RTL Design Architect Lead

Senior RTL Architect Lead Engineer Location: Bangalore Experience: 12+ Years Notice period: Immediate Seeking an experienced RTL/SoC Integration Engineer with hands-on expertise in configuring, generating, and integrating high-speed IPs such as PCIe, UCIe, and Ultra Ethernet from vendors like Synopsys, Cadence, or other third-party providers. The role involves IP bring-up, subsystem integration, and ensuring clean RTL through quality checks (lint, CDC/RDC). A candidate should have strong experience in SDC constraint development, synthesis, and timing closure, along with a solid understanding of high-speed interface protocols and SoC-level integration challenges. Translate architectural and micro‑architecture specifications into high‑quality RTL Design and implement pipelines, control logic, and datapaths Integrate synthesizable, timing‑clean, and low‑power RTL using Verilog/SystemVerilog Drive RTL quality through lint, CDC, RDC, and low‑power checks Work closely with verification teams to ensure functional closure Debug complex RTL, simulation, and post‑silicon issues Support synthesis, timing closure, and physical design teams Review RTL code and mentor junior engineers Participate in design reviews and sign‑off activities