Source description
About the role
Bachelors or Masters degree in Electronics,Electrical Engineering,Computer Engineering,or a related field. . 4 12 years of experience in ASIC / SoC Physical Design or Static Timing Analysis Experience with advanced technology nodes (16nm / 7nm/5nm / 3nm preferred). . Proficiency in TCL scripting Strong hands-on experience with Synopsys PrimeTime and / or Cadence Tempus.