PD Engineer

Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues. Solid knowledge on LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physical verification, DFM. Successful track records of taping out complex, 16nm/10nm/7nm/5nm/3nm SOC chips. Automation and programming-minded, solid coding experience in Tcl/Perl/Python. Innovative, self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English. Strong timing analysis skills. Strong physical implementation flow debugging skills. Strong scripting skills.