PD Lead

Drive the synthesis PR and Power analysis and physical verification of various SOCs align it with the design team and IP design team and external partners. Work with Product architects and Design team to Perform RTL Synthesis, PR, Physical verification, Power analysis to achieve the best Performance/Power/Area of the designs/ Timing signoff at every stage. Creating Power Intent for the designs and verify power intent on RTL, run static Low-Power checks on gate level netlists, Verify Logic Equivalency. Checks between RTL to Gates and Gates to Gates, setup signoff Static Timing Analysis and ECO flows and achieve timing closure working with the Design/DFT/PD teams. Analysis on the PR data, support the DV team to enable gate level simulations with SDF and UPF aware simulations, and support functional eco rollout with automated ECO flows. Implementation (PnR Signoff) of multimillion gate SoC designs in cutting edge process technologies (14nm, 7nm, 5nm) Physical Design including Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout. Push down the top-level floorplan and clock to Partition.IO Planning and bump planning. Evaluate low power techniques and power reduction opportunities Perform clock distribution design and analysis Perform Physical verification activities at full-chip level. Drive technical activities of physical design during technology readiness, design execution. Innovate on the flows to meet the QOR targets and ensure predictability exposure to the latest design rules, processes and innovations needed to close PPA on the advance nodes Experience handling Netlist to GDS II at Chip level for multiple takeouts Hands-on expertise with technology nodes like 7nm and below Your Background : Master degree in electrical engineering, computer engineering, or equivalent. 20+ years of experience in ARM CPU-based full-chip and subsystem SoC power aware synthesis, Timing closure Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks. Experience with Verilog and System Verilog RTL design experience with Perl/TCL/Makefile scripting. Experience with Power Analysis using Power Artist and PTPX Experience with full-chip static timing analysis through tape out, gate level simulations, and Functional ECO implementation with Automated flows. Strong communication skills are a must, as the candidate will interface with a lot of different groups within the company Ability to work well in a team and be productive under tight schedules Manage 5 to 6 member PR engineers. Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly with ICC-II, Innovus and Calibre Hands-on experience in Chip / block floor planning, placement optimizations, CTS and routing Excellent understanding and hands on experience with Chip level physical verification (DRC/LVS/ERC/antenna) and other reliability checks (IR/EM/Xtalk) Hands-on experience in block/top level signoff STA Exposure in physical implementation of timing/functional ECOs Excellent problem-solving and debugging skills.