Source description
About the role
Mandatory Knowledge/Skills/Abilities:
Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc.
Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies.
Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production.
Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis;
Must have a good understanding of device physics and the impacts of layout effects;
Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS;
Collaborative with other local or remote team members in a fast-paced professional environment.
Preferred Knowledge/Skill/Abilities:
Fluent in verbal and written communications;
Independently resolves issues and conquer design challenges;
Self-motivated and detail-oriented;
Has the knowledge of (optical) communication theories and Matlab coding.
Education and Experience Requirements:
Minimum Requirement for Principal Design Engineer: M.S. in E.E. with 8-12 years’ experience, or Ph.D. in E.E. with 4-8 years’ experience
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