Silicon Photonics PIC Architect

You will contribute to the design and development of complex photonic integrated circuits and systems for next-generation coherent transceiver technologies. As the PIC Development Engineer you will work with the PIC team and other cross-functional teams to provide the performance, power, and area estimates of the next-generation optical front-end solutions. You will assist in the development of new design approaches and work to innovate on both device-level design and system-level optimization working with cross-functional teams and collaborating to deliver co-designed and co-optimized photonics chips. You will also be responsible to deliver the manufacturing requirements of your designs, as it pertains to the foundry or OSAT limitations. You will be accountable for delivering the PICs and make design decisions as required by product specifications and schedule.

The PIC Development Engineer will be responsible for the integration of the photonic IC in optical engines and will interface with mixed signal, substrate, packaging, and simulation teams to ensure system requirements are met for co-designed and co-optimized photonics chips. This also involves:

Owning Tx and Rx PIC designs and communicating expected performance and PIC requirements to cross-functional teams. Evaluate optical link budgets, RF performance and power consumption and verify performance compared to requirements.

Defining test requirements and collaborate with test team to prepare test plans that provide coverage and address requirements.

Defining PIC reliability requirements and collaborate with reliability team to generate reliability plans.

Owning and generating PIC performance documents to track performance across R&D and production design variants.

Managing the overall system PIC fabrication and assembly track, closely interacting with the involved teams. Interact with fabrication partners and product engineering team.

Help Evaluate new design approaches and innovate on both device-level design and system-level optimization.

Contributing expertise to experimental evaluation of the integrated photonic devices/systems solutions (i.e., assessing feasibility/risk of integrating hybrid devices).

Leading task force of designers to support the design of active photonic device components for next-generation development for hybrid-integration, III-V, and L-band programs.