Lead Logic Design Engineer

Responsibilities

• Translate System Level Requirements into hardware block level specifications Digital design and RTL coding for the High-Speed data paths and control blocks Work with the verification team and Physical Design teams toward successful verification and implementation Review test plans

Requirements

• Strong experience of micro architecting and design of high-speed products Good Protocol exposure to either USB3.2, Display Port, MIPI, Ethernet Strong at Datapath designs, Aggregation and FSMs Good grasp on Digital design flows covering Low power using UPF, CDC, synthesis, DFT, P&R, Timing Power Estimations at the RTL level

Skills/Experience

• 7+ years’ experience in High Speed Datapath designs RTL design using Verilog, System Verilog Knowledge of complete RTL to GDS design implementation flow Bachelors/Masters in Electronics Engineering

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