Principal ASIC Design Engine

Principal ASIC Design Engineer – Digital Design

Primary Location: Hyderabad Role Summary: Role: We are seeking an experienced RTL Designer with strong expertise in micro-architecture development, RTL design, integration, and implementation of complex digital blocks/subsystems. The ideal candidate will have a proven track record of translating architectural specifications into high-quality RTL, driving designs from concept through synthesis and silicon bring-up, and collaborating closely with architecture, verification, DFT, physical design, firmware, and system teams.

The role requires deep knowledge of System Verilog/Verilog RTL design, digital design fundamentals, clock/reset architectures, low-power design techniques, and performance-driven implementation. The candidate should be capable of owning IP/block-level development, resolving functional and timing issues, supporting verification and implementation activities, and ensuring delivery of robust, power-efficient, and high-performance designs for next-generation AI inference accelerators.

Job Responsibility: Add a maximum of 10 bullets of key tasks in this role Key Responsibilities

Define and implement hardware architectures optimized for AI inference SoCs . Contribute to microarchitecture definition and evaluate design trade-offs for complex SoCs, including custom ISA-based processors, high-speed interconnects, and high-bandwidth I/O. Own features end to end, from specification and RTL through integration, synthesis, and debug. Collaborate with physical design teams on synthesis, timing closure, and power optimization. Work with the verification team to ensure design correctness. Partner with architecture engineers to model workloads, analyze performance bottlenecks, and validate AI inference use cases.

Job Qualification: Add up to 15 bullets describing the ideal candidate profile.

14+ years of experience in ASIC/SoC RTL design. Strong Verilog/SystemVerilog coding skills. Solid understanding of synthesis, timing analysis, and power analysis. Experience with lint, CDC, and RDC flows. Strong debugging and root-cause analysis skills.

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