Principal Engineer

Role Overview: You will be a Digital IP Verification Engineer with 10-15 years of experience, responsible for ensuring the first pass success of complex IPs using advanced verification languages and methodologies. You will collaborate with a diverse team to address verification challenges at the IP, SubSystem, and system levels. Key Responsibilities: - Evaluate and implement evolving verification methodologies for complex IP/SubSystem designs within demanding schedules. - Ensure quality adherence throughout the project cycle, identifying process improvements to achieve 'Zero Defect' IPs/SubSystems. - Contribute to technological innovations for personal and team growth. - Work effectively as part of a team, including local, remote, or multi-site teams. Qualification Required: - 10-15 years of experience in IP/Sub-system verification for multimillion Gate designs with multiple clocks. - Proficiency in Testbench and Testplan development for functional verification and performance analysis. - Familiarity with microcontroller architecture, ARM cores, protocols like AHB/AMBA, AXI, memory technologies, and controllers. - Experience in domains such as automotive Graphics/Vision accelerators, Serial IP controllers, and Networking protocols. - Strong knowledge of verification languages (UVM/SV/C++, Verilog/VHDL), simulators (NCSim/VCS/ModelSim/Questa), and verification methodologies. - Exposure to formal verification, assertions/SVA, functional coverage, gate level simulations, and regression management. - Ability to drive verification methodologies effectively, especially for candidates with 10+ years of experience. - Knowledge of pre-silicon validation/emulation is advantageous. Please note that the additional details about NXP in India were not included in the provided job description. Role Overview: You will be a Digital IP Verification Engineer with 10-15 years of experience, responsible for ensuring the first pass success of complex IPs using advanced verification languages and methodologies. You will collaborate with a diverse team to address verification challenges at the IP, SubSystem, and system levels. Key Responsibilities: - Evaluate and implement evolving verification methodologies for complex IP/SubSystem designs within demanding schedules. - Ensure quality adherence throughout the project cycle, identifying process improvements to achieve 'Zero Defect' IPs/SubSystems. - Contribute to technological innovations for personal and team growth. - Work effectively as part of a team, including local, remote, or multi-site teams. Qualification Required: - 10-15 years of experience in IP/Sub-system verification for multimillion Gate designs with multiple clocks. - Proficiency in Testbench and Testplan development for functional verification and performance analysis. - Familiarity with microcontroller architecture, ARM cores, protocols like AHB/AMBA, AXI, memory technologies, and controllers. - Experience in domains such as automotive Graphics/Vision accelerators, Serial IP controllers, and Networking protocols. - Strong knowledge of verification languages (UVM/SV/C++, Verilog/VHDL), simulators (NCSim/VCS/ModelSim/Questa), and verification methodologies. - Exposure to formal verification, assertions/SVA, functional coverage, gate level simulations, and regression management. - Ability to drive verification methodologies effectively, especially for candidates with 10+ years of experience. - Knowledge of pre-silicon validation/emulation is advantageous. Please note that the additional details about NXP in India were not included in the provided job description.