Senior Digital Design Engineer

You will be responsible for: - Defining and realizing digital functions on IPs, subsystem, or IC level based on required specifications - Performing design, verification, and evaluation of digital functions - Developing RTL using Verilog/SystemVerilog - Supporting verification activities, including developing simple testbenches and debugging issues - Participating in ASIC front-end design flow activities - Analyzing and debugging design issues during development - Collaborating with cross-functional teams - Documenting design and related work Qualifications required: - BSEE or equivalent is required; MSEE is a plus - Strong Verilog/SystemVerilog coding skills - Knowledge of ASIC front-end design flows - Experience in developing simple SystemVerilog/Verilog testbenches - Around +2 years of working experience Strongly desired qualifications: - Knowledge of UVM is desirable - Knowledge of C/C++, Matlab, Unix/Perl scripting, or Python - Knowledge of digital signal processing and telecom is a plus - Strong analytical and problem-solving skills, as well as hands-on lab debugging experience - Self-motivated, with excellent communication skills and ability to excel in a team environment - Ability to work with teams at remote locations across different time zones You will be responsible for: - Defining and realizing digital functions on IPs, subsystem, or IC level based on required specifications - Performing design, verification, and evaluation of digital functions - Developing RTL using Verilog/SystemVerilog - Supporting verification activities, including developing simple testbenches and debugging issues - Participating in ASIC front-end design flow activities - Analyzing and debugging design issues during development - Collaborating with cross-functional teams - Documenting design and related work Qualifications required: - BSEE or equivalent is required; MSEE is a plus - Strong Verilog/SystemVerilog coding skills - Knowledge of ASIC front-end design flows - Experience in developing simple SystemVerilog/Verilog testbenches - Around +2 years of working experience Strongly desired qualifications: - Knowledge of UVM is desirable - Knowledge of C/C++, Matlab, Unix/Perl scripting, or Python - Knowledge of digital signal processing and telecom is a plus - Strong analytical and problem-solving skills, as well as hands-on lab debugging experience - Self-motivated, with excellent communication skills and ability to excel in a team environment - Ability to work with teams at remote locations across different time zones