Senior Principal Engineer - IP Verification

As a Senior Principal Engineer - Digital IP Verification at our company, you will play a crucial role in leading and delivering first-pass success for complex Digital IP and Subsystem verification programs. Your deep expertise in advanced verification methodologies and strong ownership mindset will be essential for collaborating across multi-disciplinary and global teams. Role Overview: You will closely collaborate with System Architecture, Design, DFT, Mixed Signal, and Validation teams to address verification challenges for IPs, Subsystems, and full SoC context. Utilizing simulation, formal verification, hardware modeling, and pre/post silicon validation techniques will be key in this role. Key Responsibilities: - Lead end-to-end verification execution for complex IPs and Subsystems, ensuring high quality and first-pass silicon success - Evaluate, adopt, and deploy advanced and scalable verification methodologies - Own verification quality metrics across planning, execution, and closure phases - Drive a Zero Defect mindset through rigorous process adherence and defect prevention strategies - Analyze existing verification flows and implement improvements - Contribute to technical innovation within the team and influence methodology evolution - Collaborate effectively with local and global cross-functional teams Qualification Required: - 1520 years of hands-on experience in IP or Subsystem verification for complex, multi-million gate designs - Strong expertise in HVLs such as SystemVerilog/UVM and proficiency in C/C++ - Solid understanding of HDLs such as Verilog/VHDL - Experience with industry simulators such as VCS, NCSim, ModelSim, or Questa - Proficiency in test planning, feature traceability, and functional/performance validation - Strong knowledge of assertions (SVA), functional coverage, and regression management - Solid understanding of microcontroller architectures (ARM cores) and interconnect protocols such as AHB, AXI, AMBA - Experience in memory subsystems including SRAM, Flash, DDR, and memory controllers In this role, you will demonstrate strong ownership towards delivering high-quality IPs aligned with customer expectations and product timelines. You will take complete responsibility for deliverables, proactively manage risks, and drive closure with minimal supervision. Additionally, you will work effectively with global and cross-functional teams, fostering open communication and knowledge sharing. Your active contribution to continuous improvement, automation, and adoption of advanced verification practices will be crucial for success. As a Senior Principal Engineer - Digital IP Verification at our company, you will play a crucial role in leading and delivering first-pass success for complex Digital IP and Subsystem verification programs. Your deep expertise in advanced verification methodologies and strong ownership mindset will be essential for collaborating across multi-disciplinary and global teams. Role Overview: You will closely collaborate with System Architecture, Design, DFT, Mixed Signal, and Validation teams to address verification challenges for IPs, Subsystems, and full SoC context. Utilizing simulation, formal verification, hardware modeling, and pre/post silicon validation techniques will be key in this role. Key Responsibilities: - Lead end-to-end verification execution for complex IPs and Subsystems, ensuring high quality and first-pass silicon success - Evaluate, adopt, and deploy advanced and scalable verification methodologies - Own verification quality metrics across planning, execution, and closure phases - Drive a Zero Defect mindset through rigorous process adherence and defect prevention strategies - Analyze existing verification flows and implement improvements - Contribute to technical innovation within the team and influence methodology evolution - Collaborate effectively with local and global cross-functional teams Qualification Required: - 1520 years of hands-on experience in IP or Subsystem verification for complex, multi-million gate designs - Strong expertise in HVLs such as SystemVerilog/UVM and proficiency in C/C++ - Solid understanding of HDLs such as Verilog/VHDL - Experience with industry simulators such as VCS, NCSim, ModelSim, or Questa - Proficiency in test planning, feature traceability, and functional/performance validation - Strong knowledge of assertions (SVA), functional coverage, and regression management - Solid understanding of microcontroller architectures (ARM cores) and interconnect protocols such as AHB, AXI, AMBA - Experience in memory subsystems including SRAM, Flash, DDR, and memory controllers In this role, you will demonstrate strong ownership towards delivering high-quality IPs aligned with customer expectations and product timelines. You will take complete responsibility for deliverables, proactively manage risks, and drive closure with minimal supervision. Additionally, you will work effectively w