Sr Synthesis and Implementation Engineer

Role Overview: You will be a crucial member of the AI NPU team, responsible for translating RTL designs into optimized gate-level netlists to meet performance, power, and area targets for complex IP blocks. Key Responsibilities: - Perform logical and physical synthesis of RTL designs for digital blocks and sub-systems - Develop and implement timing constraints (SDC) for target frequencies and design performance optimization - Conduct STA, identify critical paths, and collaborate with design teams for timing closure - Execute formal verification (LEC) to ensure functional equivalency between RTL and synthesized netlists - Analyze and optimize power consumption using power analysis tools - Estimate and optimize area to meet aggressive PPA requirements - Collaborate with RTL designers, DFT engineers, and physical design engineers for seamless integration - Develop and maintain automation scripts (Tcl, Python, Perl) for synthesis flows and design analysis - Evaluate and integrate new CAD tools and methodologies for efficiency and design quality improvement - Document design constraints, methodologies, and analysis results thoroughly Qualification Required: - Bachelor's or Master's degree in VLSI or Electronics Engineering or a related field - 5+ years of relevant experience in digital ASIC/SoC design, focusing on synthesis and front-end implementation - Proficiency with industry-standard synthesis tools (e.g., Synopsys DC/FC or Cadence Genus) - Strong experience with physical synthesis and floorplanning is a plus - Strong understanding of static timing analysis (STA) concepts and tools (e.g., Synopsys PrimeTime or Cadence Tempus) - Experience with formal verification tools (e.g., Synopsys Formality, Cadence Conformal (LEC)) - Understanding of UPF, low-power design techniques, and power analysis concepts - Solid knowledge of Verilog/SystemVerilog for digital design - Familiarity with scripting languages (Tcl, Python, Perl) for automation - Knowledge of DFT (Design for Testability) principles is a plus - Excellent problem-solving skills, attention to detail, and strong communication and interpersonal skills to work effectively in a collaborative team environment across multiple time zones (Note: Additional details about NXP in India were not provided in the job description) Role Overview: You will be a crucial member of the AI NPU team, responsible for translating RTL designs into optimized gate-level netlists to meet performance, power, and area targets for complex IP blocks. Key Responsibilities: - Perform logical and physical synthesis of RTL designs for digital blocks and sub-systems - Develop and implement timing constraints (SDC) for target frequencies and design performance optimization - Conduct STA, identify critical paths, and collaborate with design teams for timing closure - Execute formal verification (LEC) to ensure functional equivalency between RTL and synthesized netlists - Analyze and optimize power consumption using power analysis tools - Estimate and optimize area to meet aggressive PPA requirements - Collaborate with RTL designers, DFT engineers, and physical design engineers for seamless integration - Develop and maintain automation scripts (Tcl, Python, Perl) for synthesis flows and design analysis - Evaluate and integrate new CAD tools and methodologies for efficiency and design quality improvement - Document design constraints, methodologies, and analysis results thoroughly Qualification Required: - Bachelor's or Master's degree in VLSI or Electronics Engineering or a related field - 5+ years of relevant experience in digital ASIC/SoC design, focusing on synthesis and front-end implementation - Proficiency with industry-standard synthesis tools (e.g., Synopsys DC/FC or Cadence Genus) - Strong experience with physical synthesis and floorplanning is a plus - Strong understanding of static timing analysis (STA) concepts and tools (e.g., Synopsys PrimeTime or Cadence Tempus) - Experience with formal verification tools (e.g., Synopsys Formality, Cadence Conformal (LEC)) - Understanding of UPF, low-power design techniques, and power analysis concepts - Solid knowledge of Verilog/SystemVerilog for digital design - Familiarity with scripting languages (Tcl, Python, Perl) for automation - Knowledge of DFT (Design for Testability) principles is a plus - Excellent problem-solving skills, attention to detail, and strong communication and interpersonal skills to work effectively in a collaborative team environment across multiple time zones (Note: Additional details about NXP in India were not provided in the job description)