Verification Engineer G3 (SoC Simulation & Functional Verification)

As an experienced Verification Engineer with over 6 years of experience, your role will involve defining and implementing comprehensive SoC verification strategies and plans covering all functional and performance aspects. You will lead the development of UVM/SystemVerilog-based verification environments for complex SoC/IP subsystems and drive end-to-end SoC verification, including integrating IP-level environments into SoC-level testbenches. Your responsibilities will include developing and maintaining test plans, test cases, and coverage models (functional, code, and assertion coverage), as well as creating and debugging test scenarios, sequences, and scoreboards to validate system functionality. You will also work on simulation, emulation, and formal verification tools to ensure design correctness, analyze failures, debug root causes, and collaborate with design teams for timely resolution. Additionally, you will drive coverage closure and sign-off criteria to ensure high-quality deliverables. Mentoring junior engineers and providing technical leadership within the verification team will be a key aspect of your role, along with collaborating closely with cross-functional teams including RTL design, architecture, firmware, and physical design. Preferred Skills: - Experience with low-power verification (UPF/CPF). - Knowledge of common SoC protocols (e.g., AXI, AHB, APB, PCIe, USB, Ethernet). - Exposure to emulation platforms (Palladium, Veloce, ZeBu, etc.). - Familiarity with formal verification methodologies. (Note: The job description did not contain any additional details about the company, so this section has been omitted.) As an experienced Verification Engineer with over 6 years of experience, your role will involve defining and implementing comprehensive SoC verification strategies and plans covering all functional and performance aspects. You will lead the development of UVM/SystemVerilog-based verification environments for complex SoC/IP subsystems and drive end-to-end SoC verification, including integrating IP-level environments into SoC-level testbenches. Your responsibilities will include developing and maintaining test plans, test cases, and coverage models (functional, code, and assertion coverage), as well as creating and debugging test scenarios, sequences, and scoreboards to validate system functionality. You will also work on simulation, emulation, and formal verification tools to ensure design correctness, analyze failures, debug root causes, and collaborate with design teams for timely resolution. Additionally, you will drive coverage closure and sign-off criteria to ensure high-quality deliverables. Mentoring junior engineers and providing technical leadership within the verification team will be a key aspect of your role, along with collaborating closely with cross-functional teams including RTL design, architecture, firmware, and physical design. Preferred Skills: - Experience with low-power verification (UPF/CPF). - Knowledge of common SoC protocols (e.g., AXI, AHB, APB, PCIe, USB, Ethernet). - Exposure to emulation platforms (Palladium, Veloce, ZeBu, etc.). - Familiarity with formal verification methodologies. (Note: The job description did not contain any additional details about the company, so this section has been omitted.)