Digital/RTL IC Design Engineer

BS/BE/MS/MTech + 2 years or equivalent experience in high-performance digital or mixed-signal IC development in advanced CMOS processes

Strong foundation in digital design concepts for complex ASICs

Hands on experience with the Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc

Strong understanding of digital design for mixed signal control loops and designing Verilog code to control analog circuits (e.g. digital backend for ADC, digital PLL, etc)

Familiarity with behavioral Verilog code, including wreals

Ability to write thorough testbenches

Basic understanding of SystemVerilog and assertions preferred

Basic understanding of signal processing – MATLAB understanding would be preferred but not mandatory

Understanding of constraints, especially for mixed-signal designs, including multiple clock domains and clock gating