Senior Digital Verification Engineer

You will be part of a Verification Team. You will be responsible for driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. You will be responsible for analysing Code Coverage, Functional Coverage and Assertions. Use industry standard tools, methodologies. Solid experience in verification of complex SoCs. Expertise in SoC Verification using SV and Verilog. Knowledge of UVM is a plus. Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification. Verification experience in complex datapath, DSP based ASICs is highly desirable. Good knowledge in gate-level simulation, and Scripting languages like Python, TCL. Excellent debugging and problem solving skills. Strong communication skills.