Staff Analog Design Engineer

Design and develop an analog IP block from definition to IP delivery Design and simulation at the block/IP level during execution phase, present the block results to review team in timely manner. Work with and provide guidance to layout engg and monitors the progress of IP block layout Work with validation, product engineering and test engineering teams to enable them to measure Si performance Own technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops Able to plan and execute the work in timely manner aligning with full chip schedule. Qualifications for Internal Candidates BS in Electrical Engineering or related 10 years of experience, or MS 8 and above years of experience Qualification Solid track record of delivering block/IP level design Understand and execute IP design, simulations methods, boundary conditions, stress and reliability simulations, PVT/PMC/SOA simulations. Good communication skills to make detailed technical presentations Good understanding of various building blocks like LDOs, gate drivers, comparators, linear regulators, gm-stages, charge pumps etc Experience in SiC/GAN/LED/Motor, Efuse and smart Switches etc is plus Strong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing Understanding of power transistor Design, Layout, and Robustness Experience in system tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation Strong verbal and written communication skills Ability to quickly ramp on new systems and processes Demonstrated strong interpersonal, analytical and problem-solving skills Ability to work in teams Design and develop an analog IP block from definition to IP delivery Design and simulation at the block/IP level during execution phase, present the block results to review team in timely manner. Work with and provide guidance to layout engg and monitors the progress of IP block layout Work with validation, product engineering and test engineering teams to enable them to measure Si performance Own technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops Able to plan and execute the work in timely manner aligning with full chip schedule.