Principal Engineer, Digital Design

Responsibilities

Own the architecture and development of the IO subsystem, ensuring configurability and reuse across multiple products Define subsystem-level specifications, interfaces, and integration strategy aligned with platform and product requirements Define and implement parameterized and Python generator-based design approaches, enabling scalable and configurable subsystem instantiation Drive the creation of automatically generated testbenches and verification environments, leveraging UVM frameworks and AI-assisted techniques Develop high-quality SystemVerilog RTL, ensuring compatibility with automated generation flows and maintainability at scale Support synthesis, STA, and timing closure activities to ensure signoff-ready designs Collaborate with verification, DFT, and physical design teams to achieve first-time right silicon Apply AI/ML techniques to improve design productivity, including code generation assistance, verification acceleration, and design space exploration Drive PPA optimization while maintaining configurability and reuse targets Establish best practices for design automation, code generation, and methodology standardization across the organization