FPGA Engineer

As an FPGA Engineer at PierSight Space, you will play a crucial role in implementing designs on FPGAs and contributing to the development of the world's largest constellation of Synthetic Aperture Radar and AIS satellites for comprehensive ocean surveillance. With 2-4 years of experience in FPGA design, you will bring your expertise in RTL coding using Verilog/SV, constraint definition, synthesis, floor planning, P&R, Timing closure, and micro-architectural design to optimize the design for power, performance, area, and timing requirements. Your responsibilities will include running unit level testing, creating block level design documentation, writing testbench and sequences in SystemVerilog, and working with lab equipment and interface protocols such as PCIE and Ethernet. Your familiarity with the latest FPGA architectures and scripting languages will be key in partitioning designs across multiple FPGAs. Exposure to verification tools like UVM and FPGA Hardware design will be advantageous. Key Responsibilities: - 2-4 years of hands-on experience in implementing designs on FPGAs - Strong expertise in RTL coding of complex designs using Verilog/SV - Expertise in all aspects of FPGA design; constraint definition, synthesis, floor planning, P&R, Timing closure - Early architectural/performance exploration through micro-architectural definition and design - Optimize the design to meet power, performance, area, and timing requirements - Run unit level testing to deliver quality code to the Design Verification Team - Create well-written block-level design documentation - Write testbench and sequences in SystemVerilog - Familiarity with lab equipment - Familiarity with interface protocols (PCIE, Ethernet) - Knowledge of the latest FPGA architectures and partitioning designs across multiple FPGAs - Exposure to scripting languages Preferred Experience: - Hands-on experience with FPGA design suite Libero - Tcl/perl/python scripting languages - Good hardware and software debugging skills - Experience running quality checks such as CDC - Experience in synthesis, static timing analysis - Experience with verification and UVM is an added advantage - Experience with FPGA Hardware design is an added advantage As an FPGA Engineer at PierSight Space, you will play a crucial role in implementing designs on FPGAs and contributing to the development of the world's largest constellation of Synthetic Aperture Radar and AIS satellites for comprehensive ocean surveillance. With 2-4 years of experience in FPGA design, you will bring your expertise in RTL coding using Verilog/SV, constraint definition, synthesis, floor planning, P&R, Timing closure, and micro-architectural design to optimize the design for power, performance, area, and timing requirements. Your responsibilities will include running unit level testing, creating block level design documentation, writing testbench and sequences in SystemVerilog, and working with lab equipment and interface protocols such as PCIE and Ethernet. Your familiarity with the latest FPGA architectures and scripting languages will be key in partitioning designs across multiple FPGAs. Exposure to verification tools like UVM and FPGA Hardware design will be advantageous. Key Responsibilities: - 2-4 years of hands-on experience in implementing designs on FPGAs - Strong expertise in RTL coding of complex designs using Verilog/SV - Expertise in all aspects of FPGA design; constraint definition, synthesis, floor planning, P&R, Timing closure - Early architectural/performance exploration through micro-architectural definition and design - Optimize the design to meet power, performance, area, and timing requirements - Run unit level testing to deliver quality code to the Design Verification Team - Create well-written block-level design documentation - Write testbench and sequences in SystemVerilog - Familiarity with lab equipment - Familiarity with interface protocols (PCIE, Ethernet) - Knowledge of the latest FPGA architectures and partitioning designs across multiple FPGAs - Exposure to scripting languages Preferred Experience: - Hands-on experience with FPGA design suite Libero - Tcl/perl/python scripting languages - Good hardware and software debugging skills - Experience running quality checks such as CDC - Experience in synthesis, static timing analysis - Experience with verification and UVM is an added advantage - Experience with FPGA Hardware design is an added advantage