Full-Chip STA Engineer

The Job Title: Full-Chip STA Engineer - 8-9 Yrs Location: Bangalore/ Hyderabad No. Of positions: 1 Experience required: 8-9 Years The Job Role: Top 3 skills:8+ years of hands-on experience in ASIC/SoC timing analysis, STA, or physical implementation flows. Strong experience with full-chip or large-block timing closure in advanced technology nodes such as 7nm, 5nm, 3nm, N3P, N2P, or similar. Solid understanding of MMMC timing, SDC constraints, clocking architecture, timing exceptions, CDC implications, and hierarchical signoff. Key Responsibilities: Own full-chip and block-level timing analysis and closure for complex SoC/ASIC designs across multiple modes, corners, and signoff scenarios. Develop, validate, and maintain timing constraints/SDC for full-chip integration, IP interfaces, clocking, resets, and timing exceptions. Perform STA for setup, hold, recovery/removal, clock gating, async paths, and interface timing. Debug and resolve timing violations related to datapath, clock path, crosstalk, noise, OCV/AOCV/POCV, derates, and variation effects. Work closely with physical design teams on placement, CTS, routing, extraction, and post-route timing optimization. Collaborate with RTL, IP, DFT, clocking, CAD, and integration teams to drive timing closure and signoff readiness. Execute timing ECOs with minimal impact to power, performance, area, congestion, and design stability Preferred Experience Qualifications: Bachelor s or Master s degree in Electrical/Electronics Engineering, VLSI, Microelectronics, Computer Engineering, or related field. 8+ years of hands-on experience in ASIC/SoC timing analysis, STA, or physical implementation flows. Strong experience with full-chip or large-block timing closure in advanced technology nodes such as 7nm, 5nm, 3nm, N3P, N2P, or similar. Solid understanding of MMMC timing, SDC constraints, clocking architecture, timing exceptions, CDC implications, and hierarchical signoff. Experience with synthesis, place-and-route, CTS, routing, extraction, SI/crosstalk, and signoff timing flows. Hands-on experience with industry-standard STA/implementation tools such as PrimeTime, Tempus, Fusion Compiler, Innovus, ICC2, StarRC, Quantus, or equivalent. Familiarity with high-performance design domains such as CPU, GPU, AI accelerator, fabric/interconnect, PCIe, DDR, multimedia, or memory subsystems is preferred. Strong scripting skills in Tcl, Python, Perl, or shell for timing analysis, automation, and report generation. Strong problem-solving, communication, and cross-functional collaboration skills. Interview Mode: Round of interviews: 2 R1: F2F R2: F2F(Both interviews will happen on the same day) Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.