Physical Design & Flow Methodology Engineer

About the job: This role sits at the core of Quadrics physical design and delivery engine. You will own PPA optimization, build scalable RTL-to-GDSII flows, and directly support customers integrating Quadrics GPNPU into their SoCs. Its a hands-on role that combines deep physical design expertise with real-world impact influencing architecture decisions, enabling customer tapeouts, and ensuring the IP meets aggressive performance, power, and area targets across nodes. If you prefer pure back-end execution with no ownership, this isnt it.ResponsibilitiesPPA Optimization & AnalysisDrive PPA optimization (timing, area, leakage, dynamic power) across process nodes and hardware configurationsApply low-power techniques (clock gating, multi-Vt, operand isolation) and tune synthesis/P&R to meet frequency and area targetsCharacterize design space and build PPA models to support customer evaluations and pre-salesPartner with RTL and architecture teams early to quantify trade-offs and influence design decisionsReference Flow DevelopmentBuild and maintain scalable RTL-to-GDSII reference flows for Quadric soft IPEnsure portability across process nodes with clear BKMs, SDC templates, floorplan scripts, and integration guidelinesDevelop automation using TCL and Python; leverage AI tools (e.g., Claude, Copilot) to improve efficiency and repeatabilityQualify EDA tool updates and benchmark QoR before integrating into the flowCustomer Integration & Tapeout SupportAct as the primary PD point of contact for customers from evaluation through tapeoutSupport adaptation of reference flows across process nodes, foundry PDKs, and customer environmentsDebug and resolve implementation issues (timing, congestion, power, flow failures)Support FAE and business teams with PPA feasibility studiesCollaboration & DocumentationWork closely with architecture, RTL, and software teams to meet PPA targetsDocument methodologies, best practices, and process node bring-up guidelinesIdeal CandidateBS/MS in Electrical Engineering, Computer Engineering, or related field7+ years of ASIC or processor IP physical design experience focused on PPA optimization and flow developmentTechnical SkillsHands-on experience with Synopsys or Cadence tools (synthesis, place & route, STA)Experience with advanced nodes (16nm and below, FinFET); multi-node exposure preferredStrong scripting skills in TCL and PythonSolid understanding of timing closure, congestion, power optimization, and MCMM analysisExperience with low-power design techniquesFamiliarity with AI-assisted coding tools (e.g., Claude, Copilot) for automation and productivityUnderstanding of DFT concepts and their physical design implicationsNice to HaveExperience delivering soft IP to external customers or supporting SoC integration through tapeoutBackground in AI accelerator, NPU, or DSP IPExposure to QoR tracking and large-scale synthesis/implementation runsWhats on OfferOpportunity to work on cutting-edge edge AI processor technologyHigh-ownership role with direct impact on PPA, product delivery, and customer successCollaborative, low-ego engineering cultureFast-paced environment with strong learning and growth potential Who can apply: Only those candidates can apply who: have minimum 7 years of experience are Electronics Engineering students Salary: Competitive salary Experience: 7 year(s) Deadline: 2026-10-20 23:59:59