Director - ASIC/SoC Design Manager

Role Overview: You will be responsible for developing next generation SoCs for mobile products and its adjacencies. Your role will involve understanding and working on all aspects of VLSI development from micro architecture and platform architecture, front end design, and design convergence. You will also oversee physical design and verification aspects. Key Responsibilities: - Full chip design for multi-million gates SoC Digital design and development (RTL) - Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure, and verification - Manage IP dependencies, planning, and tracking of all front end design related tasks - Drive the project milestones across the design, verification, and physical implementations Qualifications Required: - Minimum 17 years of solid experience in SoC design - Developing architecture and micro-architecture from specs - Understanding of various bus protocols like AHB, AXI, and peripherals like USB, SDCC - Understanding of Memory controller designs and Microprocessors is an added advantage - Understanding of Chip IO design and packaging is an added advantage - Familiarity with various bus protocols like AHB, AXI is highly desired - Ability to review top-level test plans - Expertise in Synopsys Design Compiler Synthesis and formal verification with Cadence LEC - Working knowledge of timing closure is a must - Good post-silicon bring-up and debug experience - Exposure to SoC integration and its challenges - Exposure to design verification aspects - Effective decision-making skills, even with incomplete information - Strong communication and leadership skills to ensure effective communication with Program Kindly note that the additional details of the company were not provided in the job description. Role Overview: You will be responsible for developing next generation SoCs for mobile products and its adjacencies. Your role will involve understanding and working on all aspects of VLSI development from micro architecture and platform architecture, front end design, and design convergence. You will also oversee physical design and verification aspects. Key Responsibilities: - Full chip design for multi-million gates SoC Digital design and development (RTL) - Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure, and verification - Manage IP dependencies, planning, and tracking of all front end design related tasks - Drive the project milestones across the design, verification, and physical implementations Qualifications Required: - Minimum 17 years of solid experience in SoC design - Developing architecture and micro-architecture from specs - Understanding of various bus protocols like AHB, AXI, and peripherals like USB, SDCC - Understanding of Memory controller designs and Microprocessors is an added advantage - Understanding of Chip IO design and packaging is an added advantage - Familiarity with various bus protocols like AHB, AXI is highly desired - Ability to review top-level test plans - Expertise in Synopsys Design Compiler Synthesis and formal verification with Cadence LEC - Working knowledge of timing closure is a must - Good post-silicon bring-up and debug experience - Exposure to SoC integration and its challenges - Exposure to design verification aspects - Effective decision-making skills, even with incomplete information - Strong communication and leadership skills to ensure effective communication with Program Kindly note that the additional details of the company were not provided in the job description.