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About the role
Job Requirements Job Summary:
We are looking for a highly skilled and hands on Lead Engineer to lead and drive Subsystem/SOC Design Verification for an ARM based SoC Design.
Extensive experience in SV/UVM based SOC or IP Verification.
Key Responsibilities:
• Own and delivery IP/Subsystem/SOC Testbench development, define Test plan, Test development & debug. • Strong knowledge in CPU based SOC architecture. • Develop and execute System Verilog/UVM Testbenches for SOC/IP Verification • Develop SV/UVM based SOC/IP Testbench & Implement and run directed, random, and constrained random tests • Analyze & Debug simulation failures across IP, interconnects , Subsystem & Top level, and work with RTL team for resolution. • Define Functional/Code/Assertion coverage metrics, sign-off checklist and drive to closure.
Work Experience Required Skills:
• 5+ years of hands-on experience in IP/SOC Verification with Strong SOC Architecture knowledge • Proficiency in SV/UVM based testbench development and constrain random verification. • Familiarity with standard verification tools ( VCS, Xcelium) and debug environment • Scripting skills ( Python/Perl) • Strong debugging, analytical and problem-solving skills • Experience in two or more High-Speed Interface Verification ( PCIE/USB/Ethernet/DDR*)
Optional Preferred Skills
• Exposure to Formal Verification or assertion-based verification. • Power aware verification ( UPF) • GLS & Xprop runs
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