Senior Lead Engineer - DV

Job Requirements Role Summary The Senior Lead Engineer – DV is responsible for leading and executing end-to-end design verification activities for IP, Subsystem, or SoC-level projects. This role involves technical ownership, team guidance, and close collaboration with design, architecture, and customer teams to achieve verification closure with high quality. Key Responsibilities Own and execute verification planning, execution, and closure for IP/Subsystem/SoC. Develop and maintain SystemVerilog / UVM-based verification environments. Lead testbench architecture, test case development, and constrained-random testing. Drive functional coverage, code coverage, and assertions to meet closure goals. Debug RTL and verification issues and work closely with design teams for resolution. Review and sign off on verification plans, environments, and results. Mentor and technically guide junior verification engineers. Support regression planning, automation, and CI flows. Participate in customer reviews, technical discussions, and estimations when required. Required Skills & Experience 7–9 years of experience in Design Verification. Strong expertise in SystemVerilog and UVM. Hands-on experience with IP, Subsystem, or SoC-level verification. Solid understanding of verification methodologies and closure metrics. Experience with industry-standard protocols such as AMBA (AXI, AHB, APB), PCIe, USB, Ethernet, or similar. Proficiency with EDA tools like VCS, Xcelium, Questa, Verdi/DVE. Strong debugging, problem-solving, and communication skills. Experience in mentoring or leading small teams is a plus. Experience with automotive, HPC, RISC-V, or processor-based SoCs. Knowledge of scripting (Python/Shell/Perl) for automation. Exposure to formal verification or low-power verification. Customer-facing or technical leadership experience. Education BE / BTech / MTech in Electronics, Electrical, or related disciplines.