Senior Lead - PD

Job Requirements Role: Physical Design Senior Lead Key Responsibilities Lead a team of Physical Design engineers.Own the complete PD flow:FloorplanningPower PlanningPlacementClock Tree Synthesis (CTS)RoutingTiming ClosurePhysical Verification (DRC/LVS)Coordinate with RTL, DFT, STA, Package, and Signoff teams.Track schedules, risks, and tapeout milestones.Review engineers' work and provide technical guidance.Drive closure of timing, power, area, and congestion issues.Present status updates to management and customers.Required Skills Strong knowledge of ICC2 / Innovus and signoff tools.Expertise in STA, timing closure, and physical design methodologies.Understanding of CMOS technology nodes and metal stack.Good debugging, communication, and leadership skills.Typical Experience 815+ years in Physical Design. Work Experience Required Skills Strong knowledge of ICC2 / Innovus and signoff tools.Expertise in STA, timing closure, and physical design methodologies.Understanding of CMOS technology nodes and metal stack.Good debugging, communication, and leadership skills. Job Requirements Role: Physical Design Senior Lead Key Responsibilities Lead a team of Physical Design engineers.Own the complete PD flow:FloorplanningPower PlanningPlacementClock Tree Synthesis (CTS)RoutingTiming ClosurePhysical Verification (DRC/LVS)Coordinate with RTL, DFT, STA, Package, and Signoff teams.Track schedules, risks, and tapeout milestones.Review engineers' work and provide technical guidance.Drive closure of timing, power, area, and congestion issues.Present status updates to management and customers.Required Skills Strong knowledge of ICC2 / Innovus and signoff tools.Expertise in STA, timing closure, and physical design methodologies.Understanding of CMOS technology nodes and metal stack.Good debugging, communication, and leadership skills.Typical Experience 815+ years in Physical Design. Work Experience Required Skills Strong knowledge of ICC2 / Innovus and signoff tools.Expertise in STA, timing closure, and physical design methodologies.Understanding of CMOS technology nodes and metal stack.Good debugging, communication, and leadership skills.