Source description
About the role
Job Requirements Job Requirements
Minimum qualifications
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Bachelor's degree in electrical engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
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6+ year of experience with physical design.
Preferred qualifications
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Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
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Experience with scripting languages such as Perl, Python, or Tcl.
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Experience with constraints, synthesis or clock tree synthesis (CTS).
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Experience in block/subchip level place and route for SoC or with multiple-cycles of SoC in ASIC design.
Responsibilities
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Participate in the physical design of blocks for TPU chips.
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Contribute to the design and closure of the subchip and individual blocks from RTL-to-GDS.
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Collaborate with RTL/Design and physical design (PD) teams to achieve the best power/performance/area (PPA) possible. Conduct feasibility studies for new microarchitectures as well as optimizing runs for best quality of result (QoR).
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