Technical Planning Lead

As a Technical Lead in Block Place and Route (P&R) at our company, you will play a crucial role in performing floor-planning and routing studies at both block and full-chip levels. Your responsibilities will include IO Planning, bump planning, clock distribution design, and analysis. You must possess in-depth knowledge and hands-on experience in Netlist2GDSII Implementation, covering various aspects such as Floorplanning, Power Grid Design, Placement, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), Power Integrity Analysis, Physical Verification, and Chip finishing. Key Responsibilities: - Perform floor-planning and routing studies at block and full-chip levels - Carry out IO Planning and bump planning - Design and analyze clock distribution - Implement Netlist2GDSII covering Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, and Chip finishing - Utilize experience in Physical Design Methodologies for sub-micron technology nodes of 16nm and lower - Program in Tcl/Tk/Perl to automate the design process and enhance efficiency - Hands-on experience with PNR Suite from Cadence & Synopsys (Innovus & ICC2) - Conduct Static Timing Analysis (PrimeTime SI), EM/IR-Drop analysis (PT-PX, Redhawk), and Physical Verification (Calibre) Qualifications Required: - Proven experience in Physical Design Methodologies for 16nm and lower technology nodes - Proficiency in programming with Tcl/Tk/Perl for design automation - Hands-on experience with PNR Suite from Cadence & Synopsys (Innovus & ICC2) - Familiarity with Static Timing Analysis, EM/IR-Drop analysis, and Physical Verification tools In our company, with over 25 years of experience as an engineering services provider, we believe in innovation and collaboration to overcome challenges and achieve the extraordinary. Join us and be a part of a diverse team empowered by a supportive workplace culture to drive progress in the world of technology and engineering. As a Technical Lead in Block Place and Route (P&R) at our company, you will play a crucial role in performing floor-planning and routing studies at both block and full-chip levels. Your responsibilities will include IO Planning, bump planning, clock distribution design, and analysis. You must possess in-depth knowledge and hands-on experience in Netlist2GDSII Implementation, covering various aspects such as Floorplanning, Power Grid Design, Placement, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), Power Integrity Analysis, Physical Verification, and Chip finishing. Key Responsibilities: - Perform floor-planning and routing studies at block and full-chip levels - Carry out IO Planning and bump planning - Design and analyze clock distribution - Implement Netlist2GDSII covering Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, and Chip finishing - Utilize experience in Physical Design Methodologies for sub-micron technology nodes of 16nm and lower - Program in Tcl/Tk/Perl to automate the design process and enhance efficiency - Hands-on experience with PNR Suite from Cadence & Synopsys (Innovus & ICC2) - Conduct Static Timing Analysis (PrimeTime SI), EM/IR-Drop analysis (PT-PX, Redhawk), and Physical Verification (Calibre) Qualifications Required: - Proven experience in Physical Design Methodologies for 16nm and lower technology nodes - Proficiency in programming with Tcl/Tk/Perl for design automation - Hands-on experience with PNR Suite from Cadence & Synopsys (Innovus & ICC2) - Familiarity with Static Timing Analysis, EM/IR-Drop analysis, and Physical Verification tools In our company, with over 25 years of experience as an engineering services provider, we believe in innovation and collaboration to overcome challenges and achieve the extraordinary. Join us and be a part of a diverse team empowered by a supportive workplace culture to drive progress in the world of technology and engineering.