RTL design engineer EICAT6833

Job Title : RTL design engineer Bay Area, CA

Location : Bay Area, CA (Day 1 Onsite )

Full-Time

Experience level: 3 years Candidate Roles and Responsibilities

• Collaboration with offshore team.

• IC role and offshore task coordination

• Must have 3 years experience with ASIC design activities – Verilog RTL, testcase debug, netlist checks, CDC checks, coverage analysis, timing closure, x-prop/gate level simulations. Preferred:

• Domain knowledge in PCIE/CXL, DDR, AMBA AXI/APB protocols.

• Please note: We strongly prefer the ASIC experience. If FPGA-only experience, then domain knowledge is must.

Education:

Bachelor’s Degree