Principal PCIe CXL RTL Design Engineer

Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Senior Design engineer to join our PCIe, CXL IP design team. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. This full-time position will allow the candidate to contribute to the architecture, design of next generation IPs, targeting the latest developments in PCIe and CXL standards. This position will also be involved in prototyping these IPs on cutting edge FPGAs. The candidate will work closely with local teams as well as with multi-cultural, multi-national colleagues. Responsibilities Contribute to the architecture and micro-architecture of next generation PCIe / CXL / AMBA controller IP Implement these designs in System Verilog Collaborate with the verification team to verify the IPs Participate in prototyping of the IPs in cutting edge FPGAs Qualifications RTL coding: Verilog / System Verilog Masters degree or PHD in Electrical Engineering, Computer Engineering or equivalent. 5+ years of experience with RTL Design Good English skills, communication skills, and willingness to work with an international team. Additional Desirable skills: Knowledge of PCIe / CXL Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.