DV Engineer (ASIC Verification Specialist)

Able to provide test bench architecture/microarchitecture of ASIC / FPGA device at the top level and functional blocks Build test benches and perform functional verification of RTL blocks/modules / top level and provide bug-free code Debug RTL code, root cause functional failures in RTL code Coverage driven verification Education qualification Bachelors / Masters degree in Engineering in the following disciplines Electrical Engineering Electronics Engineering Computer Science Engineering Or equivalent Skills Architecture, Microarchitecture of test benches for functional blocks top level Expert in the usage of VHDL Code Functional coverage methodologies Expert in scripting like PERL, Unix-shell scripting, etc.