Senior Principal Engineer & Chip Lead

As a highly experienced Chip design lead at Renesas, you will be responsible for driving the chip RTL design for power efficient chips. Your role will involve collaborating across architecture, verification, and physical design teams to deliver world-class semiconductor solutions. Key Responsibilities: - Actively drive the chip integration and the team to meet the project goals - Review architecture specifications, create RTL micro-arch specifications, and drive the RTL design using Verilog/SystemVerilog and industry-standard methodologies - Optimize RTL for timing, power, and area targets while ensuring design scalability - Work closely with architecture, Verification, firmware, and physical design teams during development and implementation to achieve the design targets - Collaborate with verification teams to ensure functional correctness and coverage goals - Work closely with synthesis and physical design teams for PPA analysis and design convergence - Work with DFT teams to achieve coverage goals - Contribute to methodology improvements for design implementation and timing closure - Provide technical leadership and guidance to junior engineers - Provide support to functional validation teams in post silicon debug - Collaborate with other functional teams including Verification, Validation, DFT, physical design, and emulation teams to achieve project targets - IP selection and make/buy decisions Qualifications: - BTech/MTech in Electrical/Electronic Engineering, Computer Engineering, or Computer Science with 15+ years of hardware design experience - 10 years of experience in RTL design at IP and chip level - Prior experience with CPU-based chip designs is a must - Experience in D2D protocols like UCIe or Bunch-of-wires - Experience in Design of Microcontroller and Microprocessor chips, CPU cores, Interconnect, Peripherals - Proven track record in timing closure and physically aware design flows - Strong communication skills (written and verbal), problem-solving, teamwork, attention to detail, commitment to task, and quality focus - Strong understanding of synthesis, STA, and power optimization techniques - Experience with low-power design techniques and multi-clock domain architectures - Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers - Strong domain knowledge of clocking, system modes, power management, debug, security, and other domains - Experience in more than one of Chiplets/Interconnect/CPU/NPU/GPU/Imaging/Display/Memory controller/Debug/clocking and reset design - Prior experience with any of these would be a plus: High-Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems - Can-do attitude, openness to new environment, people, and culture - Ability to propose innovative and leading-edge solutions - Strong drive & ability to coordinate work across highly experienced global teams Renesas is a top global semiconductor company striving to develop a safer, healthier, greener, and smarter world by offering product solutions in the automotive, industrial, infrastructure, and IoT markets. With a diverse team of over 21,000 professionals in more than 30 countries, Renesas actively embodies the Renesas Culture based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in diversity and inclusion, with a commitment to building a sustainable future through technology innovation. As a highly experienced Chip design lead at Renesas, you will be responsible for driving the chip RTL design for power efficient chips. Your role will involve collaborating across architecture, verification, and physical design teams to deliver world-class semiconductor solutions. Key Responsibilities: - Actively drive the chip integration and the team to meet the project goals - Review architecture specifications, create RTL micro-arch specifications, and drive the RTL design using Verilog/SystemVerilog and industry-standard methodologies - Optimize RTL for timing, power, and area targets while ensuring design scalability - Work closely with architecture, Verification, firmware, and physical design teams during development and implementation to achieve the design targets - Collaborate with verification teams to ensure functional correctness and coverage goals - Work closely with synthesis and physical design teams for PPA analysis and design convergence - Work with DFT teams to achieve coverage goals - Contribute to methodology improvements for design implementation and timing closure - Provide technical leadership and guidance to junior engineers - Provide support to functional validation teams in post silicon debug - Collaborate with other functional teams including Verification, Validation, DFT, physical design, and emulation teams to achieve project targets - IP selection and make/buy decisions Qualifications: - BTech/MTech in Electrical/Electronic E