Senior Principal Engineer / Senior Manager SoC / Chip Lead

Senior Principal Engineer / Senior Manager SoC / Chip Lead Memory Interface Division (MID) Experience 20+ Years Location US / Bangalore About the Role We are seeking a highly accomplished Senior Principal Engineer / Senior Manager Chip Lead to drive the development and execution of next-generation high-performance SoC products. This role will provide end-to-end technical leadership spanning architecture definition, SoC integration, execution planning, silicon realization, and product bring-up. The ideal candidate will have a strong track record of leading complex, advanced-node SoCs from concept through production, with deep expertise in large-scale digital integration, high-speed interfaces, and cross-functional execution. The role requires close collaboration with architecture, design, verification, physical design, DFT, firmware, package, analog, and product engineering teams to ensure successful delivery of world-class silicon products. Key Responsibilities Own end-to-end technical leadership and execution of complex SoC programs from architecture through silicon production.Drive l, integration strategy, execution schedules, risk management, and tape-out readiness.Lead cross-functional teams across digital design, verification, physical design, DFT, firmware, validation, packaging, and product engineering.Define chip-level architecture, integration requirements, performance targets, and power/area objectives.Drive technical decision-making and trade-off analysis across architecture, implementation, and product requirements.Oversee subsystem and IP integration, ensuring successful deployment of complex multi-domain SoCs.Partner with analog and SerDes teams to integrate high-speed interfaces and mixed-signal subsystems into the overall chip architecture.Lead design reviews, execution reviews, silicon readiness assessments, and post-silicon debug activities.Drive issue resolution across the development lifecycle and ensure successful first-pass silicon execution.Mentor senior engineers and provide technical leadership across multiple engineering organizations. Required Qualifications Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline.20+ years of semiconductor industry experience with substantial leadership responsibility.Proven experience as a Chip Lead, SoC Lead, Technical Program Lead, or equivalent role for large-scale ASIC/SoC products.Demonstrated success leading advanced-node SoCs, preferably at 3nm and/or 5nm technology nodes.Deep understanding of SoC architecture, integration methodologies, and full-chip development flows.Strong experience working across: RTL DesignDesign VerificationPhysical DesignDFTStatic Timing AnalysisLow-Power Design MethodologiesSilicon Bring-up and ProductizationExperience managing complex schedules, technical dependencies, and cross-functional execution across global teams.Strong communication, stakeholder management, and engineering leadership skills. Preferred Qualifications Prior experience with: High-performance switching siliconNetwork-on-Chip (NoC) architecturesData movement and interconnect fabricsHigh-bandwidth memory-centric systemsComplex multi-die or chiplet-based architecturesHands-on experience integrating: High-speed SerDes interfacesAnalog front-end (AFE) subsystemsMixed-signal IPsAdvanced PHY technologiesExperience with high-bandwidth and low-latency interconnect technologies.Knowledge of packaging technologies and signal integrity considerations for high-speed systems.Experience in AI, HPC, networking, connectivity, data-center, or memory infrastructure products.Prior exposure to UALink, Ethernet switching, switch fabrics, or similar high-performance interconnect technologies is highly desirable. Leadership Expectations Establish technical vision and execution strategy for complex SoC products.Drive alignment across architecture, engineering, and product stakeholders.Build and mentor high-performing engineering teams.Ensure engineering excellence, predictable execution, and first-silicon success.Champion best practices in SoC development, integration, and system-level design. .