Sr Mask Design Engineer

Job Responsibilities: Layout high performance Analog and Mixed Signal circuits using the latest Cadence Design Suite Perform IP level layout tasks including device placement, routing, matching techniques, shielding, guard rings, and parasitic-aware layout practices. Work at multiple levels of hierarchy, from macro level (block level) to Top-level (ESD/Pad frame) Verify connectivity and design rules with Assura, Calibre, PVS Use QRC extraction to analyze and reduce noisy/sensitive coupling Use third party tools to analyze IR drops and p2p resistance Liaise closely with analog designers on specific circuit requirements, e. g. power, matching, sensitivity, latch-up, ESD, etc. Work with CAD and CAE engineers to improve processes or features Qualifications Job Requirements: BE/BTech in Electrical or Electronic Engineering is preferred. A minimum of two to five years industry experience working on analog, power or mixed signal IC layouts A good working knowledge of Analog IC layout and verification tools Experience in routing using latest IC617 Virtuoso tools, i. e. wires, busses, pin-to-trunk, etc. Adherence to a formal layout methodology that is both robust and compatible with existing IP, thereby creating further re-useable IP blocks Good working knowledge of constraints-driven layout is useful but not essential Previous experience with BCD technology is a plus Experience in VSR and VCAR auto routing a plus Experience in schematic driven layout design, e. g. Modgens, Clones.