Sr Physical Design Engineer

Be part of the Renesas Memory Group, we are seeking a smart Junior Physical Design Engineer with strong expertise in RTL-to-GDSII implementation and experience working on complex STA timing closure. The role demands in-depth knowledge of industry-standard EDA tools and a solid grasp of timing closure and physical verification processes. Key Responsibilities: Execute full RTL-to-GDSII flow: Synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. Perform Static Timing Analysis (STA) and ensure timing closure across all design corners. Execute EM IR and physical verification checks (LVS, DRC). Collaborate closely with cross-functional teams (RTL, STA, Circuit, and DFT). Handle complex designs on 12nm and below technology nodes. Qualifications Must-Have Skills: 3-5 years of experience in VLSI physical design. Strong hands-on experience with tools: Innovus, Genus, Primetime, Calibre. Physical Design Methodologies: Floorplanning, Placement, MultiTap-CTS, Routing, STA. Tcl, tool scripting DDR design knowledge is plus.