FPGA Emulation Engineer

Job Description: Develop, integrate, and maintain FPGA-based emulation and prototyping platforms using Synopsys HAPS, Palladium, or equivalent systems. Convert complex SoC and ASIC RTL designs into emulation-ready models, including design partitioning and synthesis for multi-FPGA configurations. Perform design bring-up, hardware debug, and hardware/software co-validation using tools such as JTAG, logic analyzers, and waveform viewers. Collaborate closely with design, verification, and firmware teams to enable early software execution and system-level performance analysis. Support automation of build flows, configuration management, and regression testing for emulation environments. Analyze timing closure, resource utilization, and performance metrics to enhance emulation efficiency and stability. Document workflows, methodologies, and best practices to support team knowledge sharing and continuous improvement. Required Skills & Experience: 5+ years of hands-on experience in FPGA prototyping or hardware emulation of complex SoCs/ASICs. Strong experience with Synopsys HAPS-based platforms (HAPS-80/100 series preferred). Proficiency in Verilog/SystemVerilog for RTL design and debugging. Expertise in FPGA synthesis and place-and-route tools such as Synplify Pro, Vivado, or Quartus. Familiarity with UVM-based verification, hardware/software co-simulation, and embedded firmware bring-up. Experience using debug and analysis tools such as Identify, Verdi, or DVE. Scripting knowledge in Tcl, Python, and Shell for automation of build and validation processes. Strong understanding of SoC architectures, bus protocols (AXI, AHB, PCIe), and clock/reset domain design principles.