Verification Engineers

Role Overview: As a Design Verification Engineer, you will be responsible for developing and executing comprehensive verification strategies for complex ASIC/SoC designs, focusing on High-Speed Memory and Interface Protocols such as DDR, LPDDR, HBM, PCIe, and related technologies. Your main tasks will involve ensuring protocol compliance, functional correctness, and coverage closure. Key Responsibilities: - Strong understanding of ASIC/SoC Verification methodologies - Hands-on expertise in SystemVerilog, UVM, Assertions (SVA), Functional Coverage, and Constrained Random Verification - Strong knowledge of high-speed protocols including DDR3/DDR4/DDR5, LPDDR4/LPDDR5, HBM2/HBM3, and PCIe Gen3/4/5/6 - Experience in protocol checking and compliance verification - Understanding of memory controller and PHY architecture Qualifications Required: - Expertise in High-Speed Memory and Interface Protocols such as DDR, LPDDR, HBM, PCIe, and related technologies - Strong technical skills in ASIC/SoC Verification methodologies - Proficiency in SystemVerilog, UVM, SVA, and Functional Coverage - Experience with protocol checking and compliance verification - Knowledge of memory controller and PHY architecture Additional Company Details: (Omitting this section as there are no additional details provided in the JD) Role Overview: As a Design Verification Engineer, you will be responsible for developing and executing comprehensive verification strategies for complex ASIC/SoC designs, focusing on High-Speed Memory and Interface Protocols such as DDR, LPDDR, HBM, PCIe, and related technologies. Your main tasks will involve ensuring protocol compliance, functional correctness, and coverage closure. Key Responsibilities: - Strong understanding of ASIC/SoC Verification methodologies - Hands-on expertise in SystemVerilog, UVM, Assertions (SVA), Functional Coverage, and Constrained Random Verification - Strong knowledge of high-speed protocols including DDR3/DDR4/DDR5, LPDDR4/LPDDR5, HBM2/HBM3, and PCIe Gen3/4/5/6 - Experience in protocol checking and compliance verification - Understanding of memory controller and PHY architecture Qualifications Required: - Expertise in High-Speed Memory and Interface Protocols such as DDR, LPDDR, HBM, PCIe, and related technologies - Strong technical skills in ASIC/SoC Verification methodologies - Proficiency in SystemVerilog, UVM, SVA, and Functional Coverage - Experience with protocol checking and compliance verification - Knowledge of memory controller and PHY architecture Additional Company Details: (Omitting this section as there are no additional details provided in the JD)