Staff Engineer - IC Design

Job Title Staff Engineer - IC Design Role Summary Senior RTL/IC design engineer based in Hyderabad responsible for architecting and delivering digital IP for SoC integration. The role spans RTL development, documentation, synthesis/timing closure support, and post-silicon bring-up for communication and peripheral IP. Experience Level Level: Senior. Experience guidance: 515 years in RTL design and digital IP development. Responsibilities Primary responsibilities include designing synthesizable RTL, driving IP through integration and tape-out, and collaborating across verification, synthesis, and SoC teams. Develop synthesizable Verilog/SystemVerilog RTL for digital IP blocks. Drive IP development from specification to tape-out and support post-silicon validation. Ensure designs meet performance, power, and area (PPA) targets. Create and maintain micro-architecture, design specs, and integration guides. Collaborate with verification teams on test plans and functional debug. Support synthesis, lint, CDC/RDC verification, and timing closure activities. Work with SoC integration teams for IP integration and bring-up. Improve IP reuse, configurability, and design methodology; mentor junior engineers. Requirements Concise list of required technical skills and experience. Must-have items are listed first; preferred items are noted separately. Must-have: 515 years practical experience in RTL design and digital IP development. Strong proficiency in Verilog and SystemVerilog. Solid knowledge of digital design fundamentals: FSMs, datapaths, pipelining, and performance optimization. Experience with clock domain crossing (CDC) and reset domain crossing (RDC) issues and mitigation. Experience with synthesis and timing analysis and RTL/gate-level debugging. Familiarity with industry-standard EDA tool flows (Synopsys/Cadence/Mentor). Experience with AMBA protocols (AXI/AHB/APB). Nice-to-have: Experience developing peripheral/communication IP (SPI, UART, I2C/I3C, DMA, timers, interrupt controllers, memory controllers). Exposure to wireless subsystems (preferably WiFi / IEEE 802.11) or MAC-level architecture. Packet-processing or high-speed datapath design experience. Familiarity with security/crypto IP and advanced process nodes. Scripting skills (Python/Perl/Tcl) and experience with AI-powered productivity tools. Education Requirements Bachelor's or Master's degree in Electronics / Electrical Engineering or a related technical field. About the Company Company: Silicon Labs Headquarters: Austin, Texas, USA Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities. Date Posted: 2026-07-30 .