Padmi

MTS, DDR Design Verification

BangalorePosted 2 months ago
Electrical Electronics And Computer Hardware EngineeringSeniorFull Time
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Brief Description SiMa.ai™ is scaling Physical AI in Robotics, Automotive, Industrial, Aerospace and Defense, and Medical markets. We have created the industry's best purpose-built, software centric Physical AI HW/SW platform that leads the industry in Ease of use, performance, and power efficiency. SiMa.ai is led by technologists and business veterans backed by a set of top investors committed to helping customers bring ML on their platforms. SiMa.ai was founded in 2018, has raised $355M and is backed by Fidelity Management & Research Company, Maverick Capital, Point72, MSD Partners, VentureTech Alliance and more. For more information, visit https://sima.ai/ . Description Job Title: MTS, DDR Design Verification Job Location: Bangalore, India (This position requires a full-time, on-site presence in our Bangalore, India Office) Job ID: AI2494 Job Description: As the DDR Design Verification Engineer, you will participate in definition and develop the verification methodology for SiMa.ai's MLSoC™. You will be responsible for developing DDR test plans, test-benches (drivers, monitors and checkers/scoreboard etc..) and test cases. You will be executing test plans to verify the MLSoC - DDR functionality, performance and coverage analysis. You will work closely with the Architecture, RTL/uArch, and cross-functional teams. Opportunity to participate on DDR bring up on MLSoC Silicon in the lab. Required Background: BS in Computer Science/EE with 10+ years of experience or MS in computer science/EE with 8+ years of experience in SoC design verification. Experience with block level, cluster level or chip/SoC level verification. Proficiency in system verilog, UVM, constrained random and coverage driven verification methodology. DDR controller and/or DDR-IO verification experience is a must. Very good understanding of LPDDR JDEC specifications preferably for LPDDR5. Good understanding of DDR controller and phy functionality. Experience with development of test bench components, test plans for DDR/LPDDR IP verification. Good system verilog programming, debug and problem solving skills. Scripting languages, python or Perl is a plus. Personal Attributes: Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.

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