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About the role
Role & responsibilities Develop and maintain PDK components: device models, pcells, technology files, and DRC/LVS/PEX rule decks Validate PDK releases against foundry documentation, reference structures, and internal design benchmarks Support HBT and GaAs process technologiesdevice characterization, model fitting, and layout-aware design rules for RF applications Enable foundry technologies at 22nm and above nodes for analog/mixed-signal design IPs Collaborate with foundries, internal process teams, and design groups to resolve PDK gaps and drive closure on open issues Build regression and QA infrastructure for PDK releases; maintain version control and release notes Preferred candidate profile M.Tech/M.E./M.S. in EE/CE or equivalent from a reputed university 35 years in PDK development, technology enablement, and CAD/methodology for analog/mixed-signal design Hands-on experience with Cadence Virtuoso flows (OA database, pcells, techfile, rule deck integration) Strong understanding of semiconductor device physics for analog/RF: MOS, bipolar/HBT, passive structures, and process corners Experience with DRC/LVS/PEX deck development or validation in a production PDK environment Proficiency in SKILL and/or Python for PDK automation and QA scripting Ability to read and interpret foundry design manuals, DRMs, and model documentation Detail-oriented approach to release management, versioning, and issue tracking
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