Senior ASIC Digital Design Engineer

ASIC Digital Design, Sr Staff Engineer General Information Job Title ASIC Digital Design, Sr Staff Engineer Job ID 17881 Country India City Noida Date Posted 11-Jun-2026 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote Eligible No Descriptions & Requirements Job Description and Requirements Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are Leading a verification effort does not mean delegating and disappearing. You are in the code, in the debug sessions, in the coverage reviews. You can switch from mentoring an engineer through a UVM sequence to root-causing a protocol violation in a waveform viewer without losing momentum. You have built testbenches that other teams actually want to reuse, not because they were over-engineered, but because they were clear, maintainable, and got the job done. At Synopsys, you will work on IP that goes into AI accelerators, automotive SoCs, and data center silicon. The bugs you catch matter. The verification strategies you define will shape how teams work across the company. What You'll Be Doing Lead verification ownership for critical IP subsystems, defining strategy and driving execution with a team of verification engineers across Noida and global sites Build and evolve subsystem-level UVM testbenches in System Verilog, integrating RTL, behavioral models, and protocol checkers for complex multi-interface designs Write and debug advanced test scenarios, assertions, and checkers that catch the corner cases others miss, especially around DDR, HBM, PCIe, UCIe, Ethernet, or UALink protocols Define comprehensive verification test plans with clear coverage goals, track functional and code coverage metrics, and drive closure to signoff Manage regression suites, debug simulation failures, perform root cause analysis, and ensure issues are resolved before they propagate downstream Collaborate directly with RTL designers and architects to clarify specs, challenge assumptions, and ensure functional correctness from the start Mentor verification engineers on UVM methodology, debugging techniques, and verification best practices, raising the bar across the team The Impact You Will Have Catch critical design bugs early in subsystem IP that powers AI training chips, automotive SoCs, and cloud infrastructure, preventing costly silicon respins Shape verification methodology and tooling standards that will be adopted across Synopsys IP teams globally, influencing how thousands of engineers verify silicon Accelerate time to market for high-stakes customer programs by delivering verified, signoff-quality IP blocks on schedule Build reusable, maintainable testbench infrastructure that other teams can leverage, multiplying your impact across product lines Contribute to the technical growth of verification engineers in Noida, creating a stronger, more capable team for future programs Help Synopsys maintain its leadership position in semiconductor IP by ensuring our verification quality sets the industry benchmark What You'll Need Bachelor's or Master's in Electronics Engineering, Electrical Engineering, or Computer Science, with 10+ years of hands-on ASIC or FPGA verification experience Deep expertise building UVM-based testbenches in System Verilog for complex, multi-interface ASIC designs, not just maintaining existing environments but architecting new ones Proven track record technically leading verification efforts, including defining test plans, driving coverage closure, and delivering IP to signoff Strong experience with at least two of these protocols: DDR, HBM, PCIe, UCIe, Ethernet, or UALink, including writing protocol checkers and interface monitors Demonstrated ability to write complex assertions, functional coverage models, and debug difficult simulation failures across large, integrated testbenches Experience owning end-to-end verification deliverables, from initial planning through regression management, metrics closure, and final review signoff Hands-on proficiency extracting, analyzing, and acting on verification metrics using industry-standard coverage tools and methodologies Who You Are You can look at a coverage report, spot the three bins that actually matter, and explain to the team why closing them is worth the effort or why they are not When a simulation fails at 2am in regression, you do not wait for morning, you pull the waveform, find the root cause, and either fix it or loop in the right person with enough context to move fast You give feedback that makes engineers better, not just on what is wrong but on how to think about the problem differently next .