Sr Staff Engineer, Formal Verification

Senior Staff Formal Verification EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You AreYou have spent the better part of a decade proving that digital designs actually work, not just that they pass testbenches. Formal verification is where you live because you know that simulation can only show the presence of bugs, while formal methods can prove their absence. You have seen what happens when a corner case slips through, and you are the engineer who makes sure it does not. You understand RTL at a level that lets you read a design and immediately spot the edge cases that will break it. Temporal logic is not abstract theory to you, it is the language you use to describe what correct behavior actually means. You have worked with tools like Jasper or VC-Formal enough to know their strengths, their quirks, and when to push back on a proof that looks complete but is not. Mentoring comes naturally because you remember what it was like to debug your first failed assertion at 2am, and you would rather teach someone to set up a clean proof than fix their setup later. You can sit with a design team in Bangalore, walk through a formal verification plan, and leave them understanding not just what you are checking but why it matters. What You'll Be DoingBuild and maintain an end-to-end formal verification flow that integrates cleanly into the broader verification process, not a standalone tool that lives in a cornerCreate formal verification plans that identify the key behaviors worth proving, then develop the assertions, assumptions, and cover properties that actually close on those behaviorsGuide design and verification engineers on effective use of formal tools, reviewing setups and proofs to catch issues before they become blockersMaintain and extend assertion libraries that work for both simulation and formal contexts, ensuring consistency across verification approachesApply formal techniques like bounded model checking, induction, and abstraction to prove correctness of complex RTL designsDebug RTL when proofs fail, tracing back from a counterexample to the root cause in the design or the verification environmentTrain team members and mentor junior engineers on formal methods, assertion-based verification, and debugging strategiesThe Impact You Will HaveCatch design bugs that simulation would miss, preventing costly respins and schedule slips downstreamRaise the quality bar for digital designs across Synopsys products by making formal verification a standard part of the process, not an afterthoughtAccelerate verification closure by proving corner cases formally instead of writing thousands of directed tests hoping to hit themBuild verification infrastructure that other engineers can use effectively, multiplying your impact across the teamImprove design quality at the source by working closely with RTL designers to identify and fix issues earlyContribute to the silicon and IP solutions that power everything from AI accelerators to automotive systemsStrengthen the formal verification capability of the Bangalore team through knowledge sharing and hands-on mentorshipWhat You'll Need8+ years of industry experience in digital design or verification, with at least 5 years focused on formal verification techniquesDeep understanding of digital logic, RTL design patterns, and the synthesis and timing flows that turn RTL into gatesHands-on experience with Verilog or SystemVerilog and the ability to read and debug complex RTL quicklySolid grasp of temporal logic and assertion-based verification, including SVA or PSLExperience with at least one formal verification tool such as Jasper or VC-Formal, including setup, proof strategies, and debug .