Staff / Principal Engineer - FPGA

In this role, you will be engaged in end-to-end system development related to carrier-grade optical transmission, Ethernet switch/aggregation, and wireless product development. Your responsibilities will include working closely with the Product-Line Management team and Product Verification team to understand customer requirements, incorporating innovativeness and value-additions to product development. You will refer to standards, plan and execute module level design and verification. Additionally, you will collaborate with HW & SW architects to understand and influence module level design/architecture, and implement design changes in Verilog or SV. Validating the design and collaborating with other teams/members during the product verification cycle will also be part of your role. Key Responsibilities: - Strong digital design concepts and exposure to system design, with proficiency in high-speed FPGA designs - RTL front end design experience in Verilog and/or VHDL and/or SV is a must - Experience in micro-architecture design/development is required - Good understanding of high-performance FPGA architecture, FPGA Transceiver architecture, high-speed interfaces (PCIe, 1/10/100G Ethernet or OTU2/2e/4 or FC1-128), and high-speed memories (DDR3/4, RLDRAM) is essential - Experience in Static timing analysis, timing constraints, clock-domain crossing is necessary - Good understanding of FPGA clock architecture and hands-on experience on timing closure is crucial - Experience in verification/simulation tools is mandatory - Strong Lab-skills and high-speed FPGA debug techniques are required - Knowledge of scripting languages Perl, Python, TCL is preferred - Familiarity with encryption/authentication algorithms or protocols is a plus - Strong analytical and problem-solving skills are important - Ability to take complete ownership of a module from concept to product release - Good documentation, communication, and process skills are essential - Ability to work/interact with board-design/signal-integrity teams in development stages - Ability to interact with the software team to define and document software interfaces - Evaluate and make decisions around the use of new or existing technologies and tools - Ability to manage, guide, and mentor a small team Qualifications Required: - Bachelor's degree in Electrical/Electronic Engineering or related field - 10-18 years of experience in system development involving complex modules - Experience in carrier-grade optical transmission, Ethernet switch/aggregation, and wireless product development - Proficiency in Verilog, VHDL, and/or SV for RTL front end design - Knowledge of high-speed FPGA architecture, interfaces, and memories - Experience in verification/simulation tools and scripting languages - Strong analytical, problem-solving, and communication skills (Note: No additional details about the company were provided in the job description) In this role, you will be engaged in end-to-end system development related to carrier-grade optical transmission, Ethernet switch/aggregation, and wireless product development. Your responsibilities will include working closely with the Product-Line Management team and Product Verification team to understand customer requirements, incorporating innovativeness and value-additions to product development. You will refer to standards, plan and execute module level design and verification. Additionally, you will collaborate with HW & SW architects to understand and influence module level design/architecture, and implement design changes in Verilog or SV. Validating the design and collaborating with other teams/members during the product verification cycle will also be part of your role. Key Responsibilities: - Strong digital design concepts and exposure to system design, with proficiency in high-speed FPGA designs - RTL front end design experience in Verilog and/or VHDL and/or SV is a must - Experience in micro-architecture design/development is required - Good understanding of high-performance FPGA architecture, FPGA Transceiver architecture, high-speed interfaces (PCIe, 1/10/100G Ethernet or OTU2/2e/4 or FC1-128), and high-speed memories (DDR3/4, RLDRAM) is essential - Experience in Static timing analysis, timing constraints, clock-domain crossing is necessary - Good understanding of FPGA clock architecture and hands-on experience on timing closure is crucial - Experience in verification/simulation tools is mandatory - Strong Lab-skills and high-speed FPGA debug techniques are required - Knowledge of scripting languages Perl, Python, TCL is preferred - Familiarity with encryption/authentication algorithms or protocols is a plus - Strong analytical and problem-solving skills are important - Ability to take complete ownership of a module from concept to product release - Good documentation, communication, and process skills are essential - Ability to work/interact with board-design/signal-integrity teams in development stages - Ability t