Director, AI Hardware

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Director, AI Hardware

| Job Category | Tesla AI | | Location | Bengaluru Urban, KA | | Req. ID | 277030 | | Job Type | Full-time |

What to Expect

Overview

The Physical Design Lead owns end-to-end physical implementation of complex digital ASICs/SoCs—from netlist-in to GDSII-out. You will lead block- and chip-level P&R, timing/power/signoff closure, and a team of PD engineers, partnering closely with RTL, DFT, packaging, and foundry teams to deliver first-time-right silicon.

What You’ll Do

• Lead full-chip and block-level physical design: floorplan, power grid, placement, CTS, routing, and ECO
• Drive timing closure (setup/hold), SI, IR drop, EM, and power optimization to meet PPA targets
• Own physical verification and signoff: DRC, LVS, antenna, density, ERC, and foundry rule compliance
• Define PD methodology, flows, checklists, and best practices; improve turnaround and quality
• Plan and track schedules, milestones, and risk for PD deliverables across projects
• Mentor and guide junior/mid-level PD engineers; review floorplans, timing reports, and signoff results
• Collaborate with architecture/RTL on floorplan feasibility, timing budgets, and design constraints
• Work with DFT on scan, MBIST, and test-mode timing; support package/IO planning with packaging teams
• Interface with foundry/CAD on tech files, PDK updates, and process-related issues
• Drive ECOs post-tapeout and support silicon bring-up issues related to physical implementation
• Evaluate and deploy EDA tools, scripts, and automation for productivity and robustness

What You’ll Bring

Requirements

• Education

• Bachelor’s or Master’s in Electrical/Electronics Engineering, VLSI, or related field

• Experience

• 8–12+ years in ASIC/SoC physical design, with 2+ years leading projects or people

• Proven tapeouts in advanced nodes (e.g., 16nm/12nm/7nm/5nm/3nm or equivalent)

• Hands-on ownership of block or full-chip P&R through signoff and tapeout

• Technical Skills

• Strong command of industry EDA: Innovus/ICC2, Primetime/Tempus, StarRC/Quantus, Calibre (or equivalent)

• Deep knowledge of STA, CTS, congestion, power integrity (IR/EM), and SI

• Experience with UPF/CPF low-power design, multi-voltage domains, and power gating

• Scripting for flow automation: Tcl, Python, Perl, or shell

• Understanding of DFT constraints, IO/pad planning, and package-aware floorplanning

• Familiarity with foundry PDKs, design rules, and manufacturing constraints

• Leadership & Soft Skills

• Ability to set technical direction, prioritize, and make trade-offs under schedule pressure

• Clear communication with cross-functional and global teams

• Strong debugging, root-cause analysis, and decision-making

• Mentorship and constructive design reviews

Preferred

• Full-chip PD lead experience on multi-million-gate SoCs
• Experience with hierarchical design, hierarchical timing, and abstraction flows
• Knowledge of 3DIC/CoWoS/InFO or advanced packaging physical considerations
• Exposure to AI/ML accelerators, high-speed SerDes, or high-performance CPU/GPU blocks
• Prior CAD/methodology ownership or flow development

What Success Looks Like

• On-time tapeouts meeting timing, power, area, and foundry signoff criteria
• Predictable schedules with early risk identification and mitigation
• High-quality, maintainable PD flows adopted by the team
• Strong team capability growth through mentoring and clear standards

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