Design Lead

Job Overview Join Tessolve, a leading player in digital engineering and design services, as a Senior Verification Engineer. Contribute by verifying IP and SOC interfaces using SystemVerilog and advanced verification methodologies. Play a key role in integrating virtual interface peripherals, ensuring high-speed serial and SOC interfaces are efficiently verified. Engage in a multinational environment, contributing to advanced silicon products that serve top industry clients. Enhance your career by leveraging Tessolve's global presence and cutting-edge testing infrastructure. Job Designation : Senior Verification Engineer Years of Exp : 8 to 15 years Job Location : Global (Tessolve offices worldwide) What You'll Do Verify IP and SOC interfaces using SystemVerilog (SV) and UVM methodologies Integrate and verify virtual interface peripherals in silicon designs Ensure coverage closure, including code and functional aspects Prepare technical documentation, including testbench and test plan specifications Who You Are IP verification Using SV/UVM Interconnect Protocols: .DDR/PCIe/Mipi/USB/ Ethernet/CXL/UCI/UFS High Speed Serial Interfaces: PCIe or UCIe or USB or Ethernet or UPF or DDR Coverage Closure: Code, Functional and Toggle Tools: Synopsys VCS or Cadence Incisive Technical Documentation: Testbench Specification, Test Plan Specification Good exposure to Scripting skills like Perl or Python or Shell or TCL Bachelors in Electronics Engineering is a minimum requirement Masters in Electronics or Computer Science Engineering is an added advantage 8 to 15 years minimum Exposure to working in multi-national environment is required Excellent oral and written communication skills is a must. An attitude to learn and grow. Adaptability and flexibility are desired.