Sr. Design Engineer 1

Job Overview This Verification Engineer role focuses on IP and SoC verification using SystemVerilog/UVM with VIP integration, protocol and interface validation, and coverage closure. The position requires strong testbench development, scripting, and documentation skills, contributing to reliable silicon delivery within semiconductor or embedded systems teams in a global environment. Job Designation: Verification Engineer Years of Exp: 5 to 15 years minimum Job Location: Not specified What you'll do Develop and execute IP and SoC verification environments using SystemVerilog and UVM Integrate and validate Verification IP for interconnect and peripheral protocols Verify AHB, AXI, APB bus protocols and SOC interfaces like GPIO, SPI, I2C, UART Validate high-speed interfaces such as PCIe Gen3/4, USB, MIPI, UPF, or DDR Drive coverage closure across code, functional, and toggle domains Use industry simulators such as Synopsys VCS or Cadence Incisive for verification Produce technical documentation: testbench and test plan specifications Apply scripting (Perl, Python, Shell, TCL) to automate verification tasks Who you are Holds a Bachelor's degree in Electronics Engineering or equivalent qualification Advanced degree in Electronics or Computer Science is an advantage Experienced working within multi-national or distributed engineering teams Strong verbal and written communication and collaboration skills Detail-oriented with a focus on quality and timely delivery Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.