Sr. Design Engineer 2

Job Overview An experienced Static Timing Analysis (STA) Engineer responsible for STA and timing sign-off for complex SoC/ASIC designs, collaborating across RTL, synthesis, physical design, and verification teams. Key responsibilities include timing closure, developing SDC constraints, performing timing ECOs, clock and skew analysis, and supporting tape-out and foundry sign-off requirements. Required skills include hands-on use of STA tools (PrimeTime, Tempus, or equivalent), scripting for automation, MMMC analysis familiarity, and knowledge of synthesis and physical design flows. This role adds value by ensuring robust timing convergence and reliable silicon delivery for advanced technology node projects. Job location: Not specified; suitable for semiconductor/ASIC/SoC engineering teams. Job Designation : STA Engineer Years of Exp : 7+ years Job Location : Not specified What you'll do Perform block- and full-chip static timing analysis and timing sign-off tasks. Develop and maintain SDC constraints for pre- and post-layout stages. Analyze timing reports and debug setup, hold, and transition violations. Execute timing ECOs for functional and test modes as required. Drive timing closure across multiple PVT corners, modes, and scenarios. Conduct clock tree, skew, and path optimization analyses. Coordinate with RTL, synthesis, physical design, and verification teams. Support tape-out activities and interface with foundry for sign-off. Who you are Proficient with STA tools such as PrimeTime, Tempus, or equivalents. Knowledgeable of SDC constraints, timing checks, and ECO methodologies. Familiar with multi-mode multi-corner (MMMC) timing analysis. Comfortable with synthesis and physical design flows and implications. Skilled in scripting (Tcl, Perl, Python, or Shell) for automation tasks. Experienced with complex SoC/ASIC designs at advanced technology nodes. Strong debugging, analytical thinking, and problem-solving capabilities. Able to work independently and lead timing closure efforts effectively. Familiarity with low-power UPF flow, library characterization, or SI helpful. Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.