Source description
About the role
Requirements
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Bachelor's or Master's degree in Electrical or Communication Engineering, or equivalent
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3+ years of hands-on RTL design experience, developing units and blocks from architectural specifications
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Proven experience delivering designs under challenging Power, Performance, and Area (PPA) constraints
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Experience with verification debug, DMS and Gate-Level Simulations (GLS)
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Strong teamwork and communication skills - both written and verbal - with the ability to collaborate effectively across local and global teams
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Advantages:
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Familiarity with WiFi/BLE protocols, PHY-layer concepts, signal processing, and SoC architecture
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Experience with Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) design methodologies
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Hands-on experience with RTL synthesis, Static Timing Analysis (STA), and post-tapeout silicon activities
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Self-motivated, with a proactive approach to learning and tackling complex engineering challenges
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Working knowledge of AI-assisted development tools (e.g., GitHub Copilot, Claude Code) for code development and debugging
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Track record of using AI tools to accelerate RTL development and debug analysis
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Our offer for you:
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Benefit from a competitive salary, yearly profit sharing (dependent on company success), flexible working hours, an unlimited contract from the beginning and many additional benefits
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Join an international work environment where your ideas count and where you can thrive in a diverse culture
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Explore a world of opportunities for your personal and professional development
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