IP Design Verification Engineer - UVM SoC Embedded Processors

As an IP Design Verification Engineer at Texas Instruments, you will play a crucial role in ensuring the functional correctness of cutting-edge SoCs targeting automotive ADAS, zonal controllers, domain controllers, and industrial real-time control applications. Your responsibilities will include: - Drive verification strategy and create comprehensive test plans for IP blocks and sub-systems - Develop and enhance UVM and C-based testbenches and verification infrastructure - Develop test cases for IP performance/throughput measurement and stress testing - Triage regressions, debug simulations, and analyze coverage metrics - Work with cross-functional teams to achieve full verification closure - Participate in IP/sub-system specification activities and influence micro-architecture decisions - Design and execute reusable verification methodologies - Debug and resolve SoC integration issues in collaboration with SoC DV teams - Achieve DV signoff using SV & UVM constrained random methodology - Develop UVM components: agents, drivers, monitors, and scoreboards - Define and meet all functional coverage goals - Achieve 100% code coverage (block, expression, toggle) at IP DV level - Leverage AI-assisted verification tools for faster closure and signoff Minimum Requirements: - Bachelor's/Master's degree in Electrical Engineering, Electronics, or related field - 2-5 years of experience in IP DV, sub-system, or SoC DV - Proficiency in C, C++, SystemVerilog, SV Assertions, and scripting (Make, Perl, Python) - Strong knowledge of UVM and C-DPI methodology - Solid understanding of standard bus/interface protocols: AHB, APB, AXI - Experience with ARM Cortex M0/M33 or RISC-V based subsystems - Exposure to security hardware, cryptographic accelerators, and DMA - Knowledge of SoC architecture - Excellent debugging and problem-solving skills Preferred Qualifications: - Experience with Cadence simulation tools (Xcelium, Incisive, etc.) - Familiarity with formal verification techniques - Experience with JIRA-based project management - Strong verbal and written communication skills - Ability to collaborate effectively across architecture, design, and applications teams - Self-starter with the ability to own DV tasks end-to-end and deliver high-quality results If you are passionate about functional verification, SoC design quality, and working on technology that powers the future of automotive and industrial intelligence, Texas Instruments offers a collaborative, inclusive & innovation-driven engineering culture where you can make a significant impact. Apply now to be a part of our team! As an IP Design Verification Engineer at Texas Instruments, you will play a crucial role in ensuring the functional correctness of cutting-edge SoCs targeting automotive ADAS, zonal controllers, domain controllers, and industrial real-time control applications. Your responsibilities will include: - Drive verification strategy and create comprehensive test plans for IP blocks and sub-systems - Develop and enhance UVM and C-based testbenches and verification infrastructure - Develop test cases for IP performance/throughput measurement and stress testing - Triage regressions, debug simulations, and analyze coverage metrics - Work with cross-functional teams to achieve full verification closure - Participate in IP/sub-system specification activities and influence micro-architecture decisions - Design and execute reusable verification methodologies - Debug and resolve SoC integration issues in collaboration with SoC DV teams - Achieve DV signoff using SV & UVM constrained random methodology - Develop UVM components: agents, drivers, monitors, and scoreboards - Define and meet all functional coverage goals - Achieve 100% code coverage (block, expression, toggle) at IP DV level - Leverage AI-assisted verification tools for faster closure and signoff Minimum Requirements: - Bachelor's/Master's degree in Electrical Engineering, Electronics, or related field - 2-5 years of experience in IP DV, sub-system, or SoC DV - Proficiency in C, C++, SystemVerilog, SV Assertions, and scripting (Make, Perl, Python) - Strong knowledge of UVM and C-DPI methodology - Solid understanding of standard bus/interface protocols: AHB, APB, AXI - Experience with ARM Cortex M0/M33 or RISC-V based subsystems - Exposure to security hardware, cryptographic accelerators, and DMA - Knowledge of SoC architecture - Excellent debugging and problem-solving skills Preferred Qualifications: - Experience with Cadence simulation tools (Xcelium, Incisive, etc.) - Familiarity with formal verification techniques - Experience with JIRA-based project management - Strong verbal and written communication skills - Ability to collaborate effectively across architecture, design, and applications teams - Self-starter with the ability to own DV tasks end-to-end and deliver high-quality results If you are passionate about functional verification, SoC design quality, and working on technology that po