Field-Programmable Gate Arrays Engineer

Develop UVM-based verification environments for FPGA RTL blocks and subsystems. Write comprehensive test plans, and implement stimulus, checkers, monitors, and scoreboards. Ensure functional correctness via SystemVerilog assertions, constrained-random testing, and coverage closure. Analyze simulation failures and debug RTL with tools like QuestaSim/ModelSim/Vivado and waveform viewers. Collaborate with RTL designers and systems engineers to understand requirements and corner cases. Participate in code reviews, design documentation, and DO-254 verification artifacts. Contribute to integration and validation efforts on target hardware platforms (Xilinx/Intel FPGAs).