Memory Layout Engineer

As a Memory Compiler Layout Developer, your primary responsibility will be to design and verify Memory blocks including Array, Row/Column decoder, sense amplifier, pre-charge, and Control blocks for SRAM. Your tasks will include layout design, development, verification (LVS/DRC/Latchup), quality check, documentation, and ensuring on-time delivery of block-level layouts with acceptable quality. You will also demonstrate leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedule/milestones. Guiding junior team members, contributing to project management, and effective communication with engineering teams will be key aspects of your role. Qualifications/Requirements: - Familiarity with various levels of memory layouts from custom memory bits, leaf cells, control blocks, Read-Write, Sense Amplifiers, decoders. - Expertise in floor planning, power planning, block area estimation of memory designs or compilers. - Ability to perform leaf cell layout development and physical verification. - Knowledge of schematics, interface with circuit designer and CAD, and process development team. - Understanding of layout fundamentals such as Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc. - Strong problem-solving skills in solving area, power, performance, and physical verification of custom layout. - Experience with Cadence tools including Virtuoso schematic editor, Virtuoso layout L, XL & Verification tools like Mentor Calibre. - Leadership qualities, multi-tasking abilities, teamwork skills, and providing technical support to team members. - Self-motivated, hardworking, goal-oriented, with excellent verbal and written communication skills. - Knowledge of Skill coding and layout automation is a plus. (Note: No additional details about the company were provided in the job description.) As a Memory Compiler Layout Developer, your primary responsibility will be to design and verify Memory blocks including Array, Row/Column decoder, sense amplifier, pre-charge, and Control blocks for SRAM. Your tasks will include layout design, development, verification (LVS/DRC/Latchup), quality check, documentation, and ensuring on-time delivery of block-level layouts with acceptable quality. You will also demonstrate leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedule/milestones. Guiding junior team members, contributing to project management, and effective communication with engineering teams will be key aspects of your role. Qualifications/Requirements: - Familiarity with various levels of memory layouts from custom memory bits, leaf cells, control blocks, Read-Write, Sense Amplifiers, decoders. - Expertise in floor planning, power planning, block area estimation of memory designs or compilers. - Ability to perform leaf cell layout development and physical verification. - Knowledge of schematics, interface with circuit designer and CAD, and process development team. - Understanding of layout fundamentals such as Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc. - Strong problem-solving skills in solving area, power, performance, and physical verification of custom layout. - Experience with Cadence tools including Virtuoso schematic editor, Virtuoso layout L, XL & Verification tools like Mentor Calibre. - Leadership qualities, multi-tasking abilities, teamwork skills, and providing technical support to team members. - Self-motivated, hardworking, goal-oriented, with excellent verbal and written communication skills. - Knowledge of Skill coding and layout automation is a plus. (Note: No additional details about the company were provided in the job description.)