STA Lead Engineers

As an STA Lead Engineer, your role involves having a deep understanding and experience with STA tools such as Tempus, PrimeTime, Tweaker, and DMSA (PTECO). You should possess knowledge of timing corners, modes, process variations, and signal integrity related issues. Your responsibilities will include: - Experience in timing closure of high-frequency blocks and subsystems in the GHz range - Working on full-chip STA closure, defining mode requirements, and corners for timing closure - Understanding DFT modes requirements for timing signoff - Knowledge of physical design flow and ECO implementation - Understanding SDC constraints, OCV, AOCV, POCV analysis - Proficiency in TCL/scripting Qualifications required for this role: - Minimum of 7 years of experience in the field - Familiarity with semiconductor/VLSI industry - Expertise in using STA tools such as Tempus, PrimeTime, Tweaker, and DMSA (PTECO) - Strong understanding of timing closure, DFT modes, and physical design flow - Proficiency in TCL/scripting Please note: Interested candidates can share their CV to the email address provided. As an STA Lead Engineer, your role involves having a deep understanding and experience with STA tools such as Tempus, PrimeTime, Tweaker, and DMSA (PTECO). You should possess knowledge of timing corners, modes, process variations, and signal integrity related issues. Your responsibilities will include: - Experience in timing closure of high-frequency blocks and subsystems in the GHz range - Working on full-chip STA closure, defining mode requirements, and corners for timing closure - Understanding DFT modes requirements for timing signoff - Knowledge of physical design flow and ECO implementation - Understanding SDC constraints, OCV, AOCV, POCV analysis - Proficiency in TCL/scripting Qualifications required for this role: - Minimum of 7 years of experience in the field - Familiarity with semiconductor/VLSI industry - Expertise in using STA tools such as Tempus, PrimeTime, Tweaker, and DMSA (PTECO) - Strong understanding of timing closure, DFT modes, and physical design flow - Proficiency in TCL/scripting Please note: Interested candidates can share their CV to the email address provided.